1. Field of the Invention
The present invention generally relates to computer systems, specifically to a method and apparatus for interconnecting various computer components (i.e., peripheral devices), and more particularly to a method and system that provides for xe2x80x9chot pluggingxe2x80x9d of adapter cards while increasing the load and expansion capabilities of the bus for such systems.
2. Description of Related Art
A typical structure for a conventional computer system includes one or more processing units connected to a system memory device (random access memory or RAM) and to various peripheral, or input/output (I/O), devices such as a display monitor, a keyboard, a graphical pointer (mouse), and a permanent storage device (hard disk). The system memory device is used by a processing unit in carrying out program instructions, and stores those instructions as well as data values that are fed to or generated by the programs. A processing unit communicates with the other components by various means, including one or more interconnects (buses), or direct access channels. A computer system may have many additional components, such as serial and parallel ports for connection to, e.g., printers, and network adapters. Other components might further be used in conjunction with the foregoing; for example, a display adapter might be used to control a video display monitor, a memory controller can be used to access the system memory, etc.
Several different bus designs have been developed for interconnecting the various computer components. The original personal computer (PCs) introduced by International Business Machines Corp. (IBMxe2x80x94assignee of the present invention) used an xe2x80x9cexpansionxe2x80x9d bus referred to as the XT bus, which allowed a user to add various optional devices, such as additional memory (RAM), sound cards, telephone modems, etc. This early design was improved upon by adding more data and address lines, new interrupt lines, and direct memory-access (DMA) control lines, to create the well-known AT bus, which is also referred to as the Industry Standard Architecture (ISA) bus. The AT design allowed the microprocessor to run at a faster speed than the expansion bus. A 32-bit extension to this bus was later created, which is referred to as the Extended Industry Standard Architecture (EISA). Another 32-bit expansion bus developed by IBM is the Microchannel Architecture (MCA) bus.
In addition to the foregoing designs, several other bus designs have been developed allowing the use of a system bus which interconnects the processor and the system memory device(s), along with a separate, local bus which interconnects the peripheral devices to the system bus (using a bus bridge). Two well-known standards are the Video Electronics Standards Association (VL) bus, and the Peripheral Component Interconnect (PCI) bus. A computer system using this PCI bus includes, in addition to the physical PCI bus, a PCI host bridge circuit (PCI controller) which controls the transfer of data among the PCI bus, the central processing unit, and main memory. The PCI host bridge circuit is arranged to control the transfer of data between the primary PCI bus and the system bus.
A PCI controller exchanges data with the microprocessor either 32 bits or 64 bits at a time, depending on the implementation, and allows certain xe2x80x9cintelligentxe2x80x9d PCI-compliant adapters to perform tasks concurrently with the microprocessor, using a technique called bus mastering. The PCI specification also allows for multiplexing of the A/D bus lines, a technique that permits the A/D lines to transmit both address and data information on the same bus lines. An expansion bus controller for a system""s ISA, EISA, or MCA slots can optionally be installed as well, providing increased synchronization for all of the system""s bus-installed resources.
The PCI local bus specification, version 2.1, defines the electrical characteristics of the PCI bus. Specifically, a bus loading of ten loads is allowed (with the assumed capacitive loading, allowed timing budget, and bus timing definitions). Loads are calculated as follows: (1) each device that is physically soldered to the bus counts as a single load; and (2) each expansion slot coupled to the bus counts as two loads. Conformance to the maximum loading requirements, as indicated above, results in a maximum number of four slots (8 loads) with the remaining two loads for soldered components such as a host bridge.
In earlier computer systems, all of the peripheral components had to be connected (inserted in the PCI or ISA slots) at the time that the computer was first turned on, in order to properly register (initialize) the devices with the computer""s operating system. These devices are checked during the system""s power-on self test (POST), which includes a set of routines stored in the systems read-only memory (ROM) or firmware (also referred to as read-only storage, or ROS) that test the peripherals to see if they are properly connected and accompanied by a diagnostic numeric value, to the standard output device or standard error device (usually the display screen).
In the earlier systems, if a device were simply not present on the bus during the POST, then it would not be recognized if it was later inserted in a slot (while the computer was still running). In addition, the PCI local bus specification makes no provision for allowing cards to be inserted into a powered bus slot. Instead, those systems were required to be xe2x80x9crebootedxe2x80x9d in order to be able to communicate with and utilize the later-added devices. xe2x80x9cRebootingxe2x80x9d refers to the restarting of a computer system by reloading its most basic program instructions, viz., the operating system. A system can be rebooted using the software itself (a warm boot) or by actuating the system""s hardware, i.e., the reset or power buttons (a cold boot). After rebooting, the new device can be identified using various techniques.
More recent computer systems have the ability to recognize devices which are added to a bus while the computer is operating, that is, without having to reboot the system. One example is the xe2x80x9cplug and playxe2x80x9d specification, which allows a PC to configure itself automatically to work with peripherals. A user can xe2x80x9cplugxe2x80x9d in a peripheral and xe2x80x9cplayxe2x80x9d it without manually configuring the system. Plug and play operation requires both ROM that supports the specification, and a special expansion card. While this approach allows the system to recognize a newly added device, it is still often necessary to reset the system in order to properly initialize the device with the operating system. A further improvement in this area is the xe2x80x9chot-plugxe2x80x9d specification, wherein separate reset lines and other features are provided for each peripheral device, such that a device can be initialized with the operating system without requiring the entire system to be rebooted (this ability of the device/system is referred to as xe2x80x9chot-pluggablexe2x80x9d).
Oftentimes, users want to access more than four devices in the expansion slots, but the number of PCI devices that can be used concurrently on a PCI bus is still limited to the four available slots, even with hot plugging. It would, therefore, be desirable to provide a method and system that would increase the maximum number of slots or soldered components that could be coupled to the bus, while conforming to the maximum loading requirements thereof. It would also be advantageous to provide such a method and system that allows the removal and insertion of PCI adapter cards without powering down the system, while allowing the rest of the PCI adapters to remain operational, in an expanded slot environment. It would be further advantageous to provide an enhanced arbiter to support both increasing the number of slots supportable and also supporting the removal and insertion of PCI adapter cards without powering down the system.
It is therefore one object of the present invention to provide an improved computer system having an expansion bus which allows the addition of peripheral devices to the system.
It is another object of the present invention to provide such an expansion bus which may be used to connect a large number of peripheral devices to the remainder of the computer system, and to each other.
It is yet another object of the present invention to provide an enhanced arbiter allowing insertion and removal of PCI adapter cards on the expansion bus while allowing the rest of the system and I/O subsystem to remain powered and operational.
The foregoing objects are achieved in a method of providing an interconnection between one or more peripheral devices and a system bus of a computer system, generally comprising the steps of connecting a bridge to the system bus, connecting a primary peripheral bus to the bridge, connecting one or more peripheral devices to one or more of a plurality of secondary peripheral buses, selectively establishing and removing a connection from the primary peripheral bus to one of the secondary peripheral buses, and determining a target from among the one or more peripheral devices when the bridge is a master of the primary peripheral bus using an address decoder. Access to and from the primary peripheral bus can be controlled using an enhanced arbiter to select a master for the primary peripheral bus from among the one or more peripheral devices, to allow both (i) selective establishing and removing of a connection from the primary peripheral bus to one of the secondary peripheral bus segments in response to the selection of the master, and (ii) isolating of the master prior to executing a hot plug action. For peer-to-peer communications, transactions may be handled using the bridge as an agent.
Bus switch control logic is utilized to connect the target to be selected to the appropriate secondary peripheral bus segment. The bus switch control logic opens at least one switch to another one of the secondary peripheral buses that is not connected to the target, and closes a switch to the secondary peripheral bus that is connected to the target using the bus switch control logic. A peripheral device on the other one of the secondary peripheral buses detects removal of a request grant signal, and then concludes its data transfer operation.
The peripheral device may be connected to one of the secondary peripheral buses by inserting the peripheral device into the slot. Means are provided to isolate the slot from the secondary peripheral bus before inserting the device, and for applying a reset signal to the slot and initializing the peripheral device following release of the reset signal.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.